hisi-dram

記錄一下更換RAM遇到問題

更新記錄

item	note
20170123	第一版

結論

修改RAM大小需要，同時變更uboot register設定
這邊採用SDK裡面的2GB設定檔(這個外部的RAM設定為4Gb大小)

問題-無法由fastboot燒錄成功

目前將板子RAM大小
由1Gb,1Gb,2Gb,2Gb (此時uboot reg設定為768Mbyte)
改為4Gb,4Gb,4Gb,4Gb此時無法由fastboot燒錄成功

解決方式

修正uboot reg設定如下

register	xm(768Mb)	uboot-DDR466M-2GB	note
AXI_REGION_MAP (0x100)	0x1500	0x1600	DCM0 size 512MB -> 1GB , offset 0
AXI_REGION_MAP (0x110)	0x1420	0x1640	DCM1 size 256M -> 1GB , offset 1GB
AXI_REGION_ATTRIB (0x114)	0x71051024	0x71052028	DCM1偏移地址 = 256MB -> 512MB
DDRC_CFG_RNKVOL (0x8060)	0x132	0x142	DCM0 row addr: 2Gb -> 4Gb
DDRC_CFG_RNKVOL (0x9060)	0x122	0x142	DCM1 row addr: 1Gb -> 4Gb
DDRC_CFG_TIMING1 (0x8104)	0x4034b441	0x4034b48d	0x41 -> 0x8d
DDRC_CFG_TIMING1 (0x9104)	0x4034b441	0x4034b48d	0x41 -> 0x8d

當DRAM Size增加時，需要增加AREF period時間
Number of wait cycles for the AREF period or AREF to the ACT command
0x41 -> 0x8d
這邊直接使用SDK裡面提供的reg檔案
Hi3536-DMEB1-uboot-DDR466M-2GB-64bit-A17-1400M-A7-900M-AXI400M.xls

問題記錄

測試多次都相同原因

SerialPort has been connencted, Please power off, then power on the device.
If it doesn't work, please try to repower on.
###################################### ---- 10%
##################################### ---- 20%
##################################### ---- 30%
##################################### ---- 40%
##################################### ---- 51%
##################################### ---- 61%
##################################### ---- 71%
##################################### ---- 81%
##################################### ---- 91%
##############################Failed to send tail frame!
Failed to download File!

修正後如下

fastboot

SerialPort has been connencted, Please power off, then power on the device.
If it doesn't work, please try to repower on.
###################################### ---- 10%
##################################### ---- 20%
##################################### ---- 30%
##################################### ---- 40%
##################################### ---- 51%
##################################### ---- 61%
##################################### ---- 71%
##################################### ---- 81%
##################################### ---- 91%
############################## ---- 100%
Boot download completed!
￷     

U-Boot 2010.06-dirty (Jan 24 2017 - 06:58:03)

Check spi flash controller v350... Found
Spi(cs1) ID: 0xC2 0x20 0x1A 0xC2 0x20 0x1A
Spi(cs1): Block:64KB Chip:64MB Name:"MX25L512"
In:    serial
Out:   serial
Err:   serial
start download process.

Boot Started successfully!

Send command:	getinfo version
version: 3.0.3
[EOT](OK)

Send command:	getinfo bootmode
spi
[EOT](OK)

Send command:	getinfo spi
Block:64KB Chip:64MB*1 
ID:0xC2 0x20 0x1A 
Name:"MX25L512"
[EOT](OK)

Send command:	sf probe 0
65536 KiB hi_sfc at 0:0 is now current device
[EOT](OK)

Send command:	sf erase 0x0 0x60000

Erasing at 0x10000 --  16% complete.
Erasing at 0x20000 --  33% complete.
Erasing at 0x30000 --  50% complete.
Erasing at 0x40000 --  66% complete.
Erasing at 0x50000 --  83% complete.
Erasing at 0x60000 -- 100% complete.
[EOT](OK)

Send command:	sf write 0x41000000 0x0 0x60000

Writing at 0x10000 --  16% complete.
Writing at 0x20000 --  33% complete.
Writing at 0x30000 --  50% complete.
Writing at 0x40000 --  66% complete.
Writing at 0x50000 --  83% complete.
Writing at 0x60000 -- 100% complete.
[EOT](OK)Boot burned successfully.

uboot

U-Boot 2010.06-dirty (Jan 24 2017 - 06:58:03)

Check spi flash controller v350... Found
Spi(cs1) ID: 0xC2 0x20 0x1A 0xC2 0x20 0x1A
Spi(cs1): Block:64KB Chip:64MB Name:"MX25L512"
In:    serial
Out:   serial
Err:   serial
*** ver different
Saving Environment to SPI Flash...
Erasing SPI flash, offset 0x00080000 size 128K ...done
Writing to SPI flash, offset 0x00080000 size 128K ...done
boot_other = 0
boot_other_cnt = 0
boot_curr = 0
Hit any key to stop autoboot:  0 
65536 KiB hi_sfc at 0:0 is now current device

block_size : 1927463610
rootfs_size : 1927463610
execute sf read 0x42000000 0x72efc2ba 0x40;
ERROR: read/write area is out of range!

hisilicon #

DDR Control

Hi3536

DDRC
- DDR3/DDR4 synchronous dynamic random access memory (SDRAM) controller
- Dual channels
  - each of which provides space for one DDR3/DDR4 SDRAM chip select (CS).
  - The width of the DDR3/DDR4 SDRAM data bus for each channel is 32 bits.
- Maximum 3 GB storage space (maximum 2 GB for each channel)
  支持最大存储空间为：3GByte，每个通道最大存储空间为：2GByte

DDR3 16bit採法如下

DMC0 表示通道0
DMC1 表示通道1
双通道模式下，每个通道对接 32bit DDR3 SDRAM 由两片数据总线宽度为 16bit 的存储器件组成
DDRC/DMCn 对应的命令控制信号 :
DDR_CS_N、DDR_CKE、DDR_RESET_N、DDR_RAS_N、DDR_CAS_N、DDR_WE_N、DDR_BA[2:0]、DDR_A[15:0]、DDR_ODT

地址映射方式

SDRAM中，两种不同的地址映射方式
- BRC = Bank, Row, Column = Bank-Row-Column
- RBC = Row, Bank, Column = Row-Bank- Column
RBC模式示例说明
- AXI_REGION_ATTRIB[ch_mode]=2’b01
- 地址映射关系为
- DDRC_CFG_RNKVOL[mem_map]为 2b00, RBC映射方式
  BUSADR[m-1:0] = {DDRROW[x-1:0],DDRBA[z-1:0],DDRCOL[y-1:0],DW{b0}}
- DDRC_CFG_RNKVOL[mem_map]为 0b01时，BRC映射方式
  BUSADR[m-1:0] = {DDR_BA[z-1:0],DDRROW[x-1:0],DDRCOL[y-1:0],DW{b0}}

DDRC DDR3 32bit模式地址映射表
表格示例说明了RBC模式下的地址映射关系

比較RegBit

mddrc_dmc (0x1211 0000)

TIMMING 1_1

register	xm(768Mb)	2G bit	4Gbit
AXI_REGION_MAP (0x100)	0x1500	0x1600	0x1700
AXI_REGION_MAP (0x110)	0x1420	0x1640	0x1780
AXI_REGION_ATTRIB (0x104)	0x71050028	0x71050028	0x71050028
AXI_REGION_ATTRIB (0x114)	0x71051024	0x71052028	0x71054028
DDRC_CFG_RNKVOL (0x8060)	0x132	0x142	0x152
DDRC_CFG_RNKVOL (0x9060)	0x122	0x142	0x152
DDRC_CFG_TIMING1 (0x8104)	0x4034b441	0x4034b48d	0x4034b48d
DDRC_CFG_TIMING1 (0x9104)	0x4034b441	0x4034b48d	0x4034b48d
DDRC_CFG_TIMING2 (0x8108)	0x64011000	0x64011000	0x6400d000
DDRC_CFG_TIMING2 (0x9108)	0x64011000	0x64011000	0x6400d000

xm-768MB -> xm-4GB

register	xm-768MB	xm-4GB	note, xm->4GB
AXI_REGION_MAP (0x100)	0x1500	0x1700	DCM0 size 512MB -> 2GB , offset 0
AXI_REGION_MAP (0x110)	0x1420	0x1780	DCM1 size 256M -> 2GB , offset 2GB
AXI_REGION_ATTRIB (0x114)	0x71051024	0x71054028	DCM1 offset 256M -> 1024MB, 映射到双通道, (xm映射到单通道?)
DDRC_CFG_RNKVOL (0x8060)	0x132	0x152	DCM0 row bit : 14bit(2Gb) -> 16bit(8Gb)
DDRC_CFG_RNKVOL (0x9060)	0x122	0x152	DCM1 row bit : 13bit(1Gb) -> 16bit(8Gb)
DDRC_CFG_TIMING1 (0x8104)	0x4034b441	0x4034b48d	Number of wait cycles for the AREF period or AREF to the ACT command , 0x41 -> 0x8d
DDRC_CFG_TIMING1 (0x9104)	0x4034b441	0x4034b48d	0x41 -> 0x8d
DDRC_CFG_TIMING2 (0x8108)	0x64011000	0x6400d000	Number of clock cycles for four consecutive activation commands, 0x11 -> 0x0d
DDRC_CFG_TIMING2 (0x9108)	0x64011000	0x6400d000	0x11 -> 0x0d

DDRC_CFG_TIMING1/2: 0x41
muxctrl_reg39-54 : 0

mddrc_dmc

AXI_REGION_MAP

[10:8] rgn_size
[7:0] rgn_base_addr
0x0100
- [10:8]
- 4(100) , 256B (DMC0)
- 5(101) , 512B (DMC0)
- 6(110) , 1GB (DMC0)
- 7(111) , 2GB (DMC0)
0x0110
- [7:0] Base address of the current address area (upper eight bits)
- 0x420 , 32 x 16MB = offset 512MB(DMC0) , 256MB(DMC1)
- 0x640 , 64 x 16MB = offset 1024MB(DMC0) , 1GB(DMC1)
- 0x780 , 128 x 16MB = offset 2048MB(DMC0) , 2GB(DMC1)

512MB(DMC0) , 256MB(DMC1) => 768MB
1024MB(DMC0) , 1GB(DMC1) => 2GB
2048MB(DMC0) , 2GB(DMC1) => 4GB ,最大3Gbyte

AXI_REGION_ATTRIB

AXI_REGION_ATTRIB
xm 2G
0x104 => 0x71050028, 0x71050028
0x114 => 0x71051024, 0x71052028

[30:28] bnk_mod, 7
[25:24] rnk_mod, 1(单 RANK地址独立) ,
[18:16] addr_aligned, 5(101), 256Byte
[15:8] ch_offset ,当前地址区域在通道内的偏移地址(高八位)
0x10 , 16 x 16M , DCM1偏移地址 = 256MB , xm-768M
0x20 , 32 x 16M, DCM1偏移地址 = 512MB , 2GB
0x40 , 64x 16M, DCM1偏移地址 = 1024MB ,4GB
Bits [31:24] of the 32-bit address after channel mapping can be replaced
[5:4] ch_intlv, Address interleaving granularity of the current address area
2(10) , 512Byte, 当前地址区域的地址交织粒度(单通道地址独立模式下，此配置无效)
[3:2] ch_mod, Channel mapping mode of the current address area
(10) The addresses of two channels are mapped to the channel, and the addresses are interleaved
2GB,4GB 映射到双通道
(01) 0x1: The address of a single channel is mapped to the channel, and the address is independent
XM 映射到单通道
[1:0] ch_start,Mapping start channel of the current address area
(00) channel 0

DMC registers

DMC0 base address: 0x1211_8000
DMC1 base address: 0x1211_9000

DDRC_CFG_RNKVOL	xm (768MB)	2GB	4GB
0x8060	0x132	0x142	0x152
0x9060	0x122	0x142	0x152

DDRC_CFG_RNKVOL
DDRC-controlled DDR capacity configuration register
- [16] mem_x4 : 4-bit external component combination mode
  0: 8-/16-/32-bit external components are combined
- [13:12] mem_map, Address translation mode of the SDRAM
  00: {Rank, Row, Ba, Col, DW} = AXI_Address
- [9:8] Number of banks of a single SDRAM
  01: 8 bank
- [6:4] Bit width of the row address of a single SDRAM
  2(010): 13bit xm DCM1 ,1Gb
  3(011): 14bit xm DCM0 ,2Gb
  4(100): 15bit DCM0,DCM1 4Gb? (2Gb ,開啟dual bank,變成2GB 64bit??)
  5(101): 16bit DCM0,DCM1 8Gb? (4Gb,開啟dual bank,變成4GB 64bit? ?)
- [2:0] Bit width of the column address of a single SDRAM
  2(010): 10bit

DDRC_CFG_TIMING1

register	xm(768Mb)	2G bit	4Gbit
DDRC_CFG_TIMING1 (0x8104)	0x4034b441	0x4034b48d	0x4034b48d
DDRC_CFG_TIMING1 (0x9104)	0x4034b441	0x4034b48d	0x4034b48d

[31:24] , tsre, Number of wait cycles from the self-refresh exit command to the read command
0x40
[23:20] ,trtw,Delay from the last read data command to the first write data command
3
[19:15], twl, Number of wait cycles from the write command to the write data command
(1001)
[14:10] , tcl, Column address strobe (CAS) latency from the read command to the read data operation
(1101)
[8:0], trfc, Number of wait cycles for the AREF period or AREF to the ACT command
0x8d , 141 (sdk-2G,4G)
0x41 , 65 (xm-768)

DDRC_CFG_TIMING2

[31:28], tcke, Minimum cycle of retaining the self-refresh mode
0x6 (6 clock cycles)
[27:24], twtr, Number of wait cycles for the last write data to the write-to-read command
0x4 (4 clock cycles)
[17:12], tfaw, Number of clock cycles for four consecutive activation commands
0x11 (17 ,2Gb)
0x0d (13 ,4Gb)

mddrc_phy0 / mddrc_phy1

mddrc_phy0

TIMMING 1_2

register	xm(768Mb)	2G bit	4Gbit
DMSEL(0xc084)	0x00430a	0x00430a	0x00504b05

xm-768MB -> xm-4GB

register	xm-768MB	xm-4GB	note, xm->4GB
DMSEL(0xc084)	0x00430a	0x00504b05	無相關datasheet, 0x00430a ->0x00504b05

mddrc_phy1

TIMMING 1_3

register	xm(768Mb)	2G bit	4Gbit
DMSEL(0xe084)	0x00430a	0x00430a	0x00504b05

xm-768MB -> xm-4GB

register	xm-768MB	xm-4GB	note, xm->4GB
DMSEL(0xe084)	0x00430a	0x00504b05	無相關datasheet, 0x00430a ->0x00504b05

ddr0_training

0x1211c000

TIMMING 1_4

register	xm(768Mb)	2G bit	4Gbit
ACCMDBDL4(0x1048)	0x31	0x31	0x2F
MISC (0x70)	0x0	0x0	0x1220
LDQSSEL (0x1208)	0x0002FF00	0x0002FF00	0x000155AA
HDQSSEL (0x1308)	0x0002FF00	0x0002FF00	0x000155AA

xm-768MB -> xm-4GB

register	xm-768MB	xm-4GB	note, xm->4GB
ACCMDBDL4(0x1048)	0x31	0x2F	無相關datasheet, 0x31 ->0x2F
LDQSSEL (0x1208)	0x0002FF00	0x000155AA	0x0002FF00 -> 0x000155AA
HDQSSEL (0x1308)	0x0002FF00	0x000155AA	0x0002FF00 -> 0x000155AA

ddr1_training

0x1211e000

TIMMING 1_5

register	xm(768Mb)	2G bit	4Gbit
MISC (0x70)	0x0	0x0	0x1220
LDQSSEL (0x1208)	0x0002FF00	0x0002FF00	0x0001FF00
HDQSSEL (0x1308)	0x0002FF00	0x0002FF00	0x000155AA

register	xm-768MB	xm-4GB	note, xm->4GB
MISC (0x70)	0x0	0x1220	0x0 -> 0x1220
LDQSSEL (0x1208)	0x0002FF00	0x0001FF00	0x0002FF00->0x0001FF00
HDQSSEL (0x1308)	0x0002FF00	0x000155AA	0x0002FF00 -> 0x000155AA

TIMMING 1_6

register	xm(768Mb)	2G bit	4Gbit
DDRC_CFG_TIMING2 (0x8108)	0x64011000	0x640110e0	0x6400d0e0
DDRC_CFG_TIMING2 (0x9108)	0x64011000	0x64011000	0x6400d000

muxctrl_reg

0x120f0000

reg	xm	2Gb	4Gb
muxctrl_reg39(0x9C) DQ0	0	0	2
muxctrl_reg40(0xA0) DQ1	0	0	2
muxctrl_reg41(0xA4) DQ2	0	0	2
muxctrl_reg42(0xA8) DQ3	0	0	2
muxctrl_reg43(0xAC) DQ4	0	0	2
muxctrl_reg44(0xB0) DQ5	0	0	2
muxctrl_reg45(0xB4) DQ6	0	0	2
muxctrl_reg46(0xB8) DQ7	0	0	2
muxctrl_reg47(0xBC) DQ8	0	0	3
muxctrl_reg48(0xC0) DQ9	0	0	2
muxctrl_reg49(0xC4) DQ10	0	0	2
muxctrl_reg50(0xC8) DQ11	0	0	2
muxctrl_reg51(0xCC) DQ12	0	0	2
muxctrl_reg52(0xD0) DQ13	0	0	2
muxctrl_reg53(0xD4) DQ14	0	0	2
muxctrl_reg54(0xD8) DQ15	0	0	2

reg	00b	01b	10b	11b
muxctrl_reg39(0x9C)	NF_DQ0	VI_DATA0	SDIO1_CCLK_OUT	GPIO10_0
muxctrl_reg40(0xA0)	NF_DQ1	VI_CLK	SDIO1_CCMD	GPIO10_1
muxctrl_reg41(0xA4)	NF_DQ2	VI_DATA1	SDIO1_RSTN	GPIO10_2
muxctrl_reg42(0xA8)	NF_DQ3	VI_DATA2	SDIO1_DS	GPIO10_3
muxctrl_reg43(0xAC)	NF_DQ4	VI_DATA3	SDIO1_CDATA6	GPIO10_4
muxctrl_reg44(0xB0)	NF_DQ5	VI_DATA4	SDIO1_CDATA5	GPIO10_5
muxctrl_reg45(0xB4)	NF_DQ6	VI_DATA5	SDIO1_CDATA3	GPIO10_6
muxctrl_reg46(0xB8)	NF_DQ7	VI_DATA6	SDIO1_CDATA4	GPIO10_7
muxctrl_reg47(0xBC)	NF_RDY0	VI_DATA7	X	GPIO4_4
muxctrl_reg48(0xC0)	NF_RDY1	VI_DATA8	SDIO1_CARD_POWER_EN	GPIO4_5
muxctrl_reg49(0xC4)	NF_CSN0	VI_DATA13	SDIO1_CWPR	GPIO4_6
muxctrl_reg50(0xC8)	NF_CSN1	VI_DATA14	SDIO1_CDATA0	GPIO4_7
muxctrl_reg51(0xCC)	NF_REN	VI_DATA9	SDIO1_CDATA1	GPIO1_4
muxctrl_reg52(0xD0)	NF_WEN	VI_DATA10	SDIO1_CARD_DETECT	GPIO1_5
muxctrl_reg53(0xD4)	NF_CLE	VI_DATA12	SDIO1_CDATA2	GPIO1_6
muxctrl_reg54(0xD8)	NF_ALE	VI_DATA11	SDIO1_CDATA7	GPIO1_7

padctrl_reg

0x120f0800

reg	xm	2G	4G
PADCTRL_REG39 (0x9c),NF_DQ0	0x68	0x68 (2mA)	0x48 (5mA)
PADCTRL_REG40 (0xa0),NF_DQ1	0x28	0x28 (2mA)	0x08 (4mA)
PADCTRL_REG41 (0xa4),NF_DQ2	0x28	0x28 (2mA)	0x38 (1mA)
PADCTRL_REG42 (0xa8),NF_DQ3	0x28	0x28 (2mA)	0x38 (1mA)
PADCTRL_REG43 (0xac),NF_DQ4	0x28	0x28 (2mA)	0x08 (4mA)
PADCTRL_REG44 (0xb0),NF_DQ5	0x28	0x28 (2mA)	0x08 (4mA)
PADCTRL_REG45 (0xb4),NF_DQ6	0x28	0x28 (2mA)	0x08 (4mA)
PADCTRL_REG46 (0xb8),NF_DQ7	0x28	0x28 (2mA)	0x08 (4mA)
PADCTRL_REG47 (0xbc),NF_RDY0	0x38	0x38 (1mA)	0x38 (1mA)
PADCTRL_REG48 (0xc0),NF_RDY1	0x38	0x38 (1mA)	0x38 (1mA)
PADCTRL_REG49 (0xc4),NF_CSN0	0x38	0x38 (1mA)	0x38 (1mA)
PADCTRL_REG50 (0xc8),NF_CSN1	0x38	0x38 (1mA)	0x08 (4mA)
PADCTRL_REG51 (0xcc),NF_REN	0x18	0x18 (4mA)	0x08 (4mA)
PADCTRL_REG52 (0xd0),NF_WEN	0x18	0x18 (4mA)	0x38 (1mA)
PADCTRL_REG53 (0xd4),NF_CLE	0x28	0x28 (2mA)	0x08 (4mA)
PADCTRL_REG54 (0xd8),NF_ALE	0x28	0x28 (2mA)	0x08 (4mA)

PADCTRL_REG39
drive capability register for the NF_DQ0 pin
[6:4] Drive current of the NF_DQ0 pin
6(110) , 2mA
4(100) , 5mA
3 Level conversion rate of the NF_DQ0 pin
1: slow edge

DDR3 SDRAM Address

Size	1Gb	2Gb	4Gb
Configuration	64Mbx16	128Mbx16	256Mbx16
of Bank	8	8	8
Bank Address	BA0-2	BA0-2	BA0-2
Row Address	RA0-12	RA0-13	RA0-14
Column Address	CA0-9	CA0-9	CA0-9

K4G2G1646C Datasheet

K4B4G1646D-BCKO

K4B4G1646D-BCKO

DRAM Type	Density	Bit Organization	internal banks	interface	Revision	Pakcage Type	Temp & Power	Speed
K4B	4G	16	4	6	D	B	C	KO
	4G bit	x16 ( 256Mbit x 16bit)	8bank		D:5th Gen.	FBGA	0C-85C	DDR-1600 (800MHz),CL=11,tRCD=11,tRP=11

認識記憶體，時脈和時序的意義
DDR3顯示多少頻率MHZX2 就是跑多少速度
CL: CAS Latency
tCAS (Column Address Select)
- 列位址送出，到資料取得之間的時間
- tCAS就是CAS Latency（CAS延遲），簡稱CL值
tRCD (RAS to CAS Delay)
- 送出行位址之後，到送出列位址之間的時間
tRP (RAS Prechange)
- 關閉一行，到重新啟動另一行之間的時間
tRAS(Row Address Select)
- 啟動一行需要的時間
K4B4G1646D-BCKO
- 256Mbit x 16
K4B1G1646G-BCK0 (xm)
- 64Mbit x 16
K4B2G1646G-BCK0 (xm)
- 128Mbit x 16
SDK
- DDR3 颗粒：4Gbit，16bit 位宽,933MHz
- MT41J256M16LY-091G
- 256M x 16
- Configuration: 32M x 16 x 8Bank
- Bank Address: BA2-0
- Row Address: RA0-14
- Column Address: CA0-9

參考來源

SDRAM的地址映射方式BRC(Bank Row Column)和RBC(Row Bank Column)
Hi3536 内存映射问题
認識記憶體，時脈和時序的意義
其它hisi dram相關討論
- DDR读写数据不一致
sdk board ram MT41J256M16LY-091G
xm board ram: samsung K4B1G1646D

更新記錄

目錄

結論

問題-無法由fastboot燒錄成功

解決方式

問題記錄

修正後如下

DDR Control

Hi3536

DDR3 16bit採法如下

地址映射方式

比較RegBit

mddrc_dmc

AXI_REGION_MAP

AXI_REGION_ATTRIB

DMC registers

DDRC_CFG_TIMING1

DDRC_CFG_TIMING2

mddrc_phy0 / mddrc_phy1

mddrc_phy0

mddrc_phy1

ddr0_training

ddr1_training

muxctrl_reg

padctrl_reg

DDR3 SDRAM Address

K4B4G1646D-BCKO

參考來源